Princeton University

School of Engineering & Applied Science

Delay/Power Modeling and Optimization Techniques for Low-Power FinFET Logic Circuits and Arhitectures

Aoxiang Tang
Engineering Quadrangle J401
Monday, March 30, 2015 - 4:00pm to 6:00pm

Technology scaling has been one of the most fundamental ways to improve chip performance and reduce power consumption. However, further scaling beyond the submicron regime is encountering severe difficulties because channel current is hard to be turned off due to short-channel effects (SCEs). This has led to the emergence of a 3D structure device, called FinFET. It has begun to replace traditional MOSFETs at 22nm and beyond due to its superior control over SCEs. This talk explores the performance and power consumption of FinFET devices under process, voltage, and temperature (PVT) variations, from circuit to architecture level. It provides circuit designers with accurate FinFET models and simulators to evaluate their designs implemented with this new technology.

PVT variations cause uncertainties in circuit performance and power consumption. They arise due to limitations of lithography that lead to variations in the physical dimensions of the device or due to environmental variations. This talk proposes statistical FinFET models to evaluate the power and delay deviations caused by PVT variations, taking into account spatial correlations. A multiobjective statistical FinFET logic circuit optimizer called GenFin is presented based on the statistical models. It can simultaneously optimize timing, leakage power, and dynamic power yields through gate sizing through genetic algorithm (GA). The framework includes an incremental timing analysis method as well as novel GA heuristics to speed up the analysis and optimization process.

The send part of the talk introduces a design and simulation framework, called McPAT-PVT, for accurate and fast prediction of delay and power of FinFET-based processors under PVT variations. It supports various operation temperatures and frequencies, and can be applied to different processor configurations. We rigorously investigate area, delay, and power for various functional units and caches and also explore the timing and power yields of a FinFET processor based on the Alpha processor core. Results obtained using PARSEC real traffic data are also presented. Results show that processors implemented with asymmetric shorted-gate FinFET devices have the advantage of consuming far less power with little penalty in area or timing.