Design Automation for Software Programmable FPGAs

Date
May 25, 2017, 12:30 pm12:30 pm
Location
Engineering Quadrangle, Room B205

Speaker

Details

Event Description

Systems across the computing spectrum, from edge devices to cloud datacenters, are increasingly turning to specialized hardware accelerators for improved performance and energy efficiency. Heterogeneous architectures integrating reconfigurable devices like FPGAs show significant potential in this role. However, there is still a considerable productivity gap between register-transfer-level FPGA design and traditional software design. Enabling high-level programming of FPGAs is a critical step in bridging this gap and pushing FPGAs further into the computing space. In this talk, I will briefly review the progress we have made in research and commercialization on high-level synthesis (HLS) for FPGAs. In particular, I will use a few real-life applications as case studies to motivate the need for HLS tools, and discuss their benefits and limitations. I will then describe novel synthesis algorithms in scheduling, pipelining, and mapping that can effectively handle a rich set of design constraints, and at the same time, carry out highly efficient global optimization. I also plan to outline several major research challenges in design automation for FPGA-based computing, and introduce some of our ongoing work along these directions.