Princeton University

School of Engineering & Applied Science

FinFET-based System Modeling and Low-Power System Design

Speaker: 
Xianmin Chen
Location: 
Engineering Quadrangle B327
Date/Time: 
Thursday, March 10, 2016 - 12:30pm to 2:30pm

Abstract
FinFET replaced MOSFET at the 22nm technology node and beyond. Compared to planar CMOS, FinFET has higher on-current and lower leakage due to its double-gate structure. For system architects, a FinFET-based simulation framework can be very helpful at early design stage. However, such a simulator did not exist. We present the details of one such simulation framework, called gem5-PVT. The framework leverages existing lower-level FinFET simulators to support timing, power, and thermal studies of FinFET-based chip multiprocessor (CMP) systems under process, voltage, and temperature (PVT) variations.
Another problem we target is to reduce CMP power consumption. The CMP power budget is expected to limit the portion of the chip we can power-on. With the introduction of 3-dimensional (3D) integrated circuits (ICs), it is likely to become even more severe. In this work, we propose several approaches to reduce CMP power. To reduce leakage power, we use a hybrid FinFET style to design ultra-low-leakage FinFET CPU cores. This approach exploits the ultra-low-leakage feature of asymmetric-workfunction shorted-gate (ASG) FinFETs and the high-performance feature of shorted-gate (SG) FinFETs. We explore the impact of the hybrid style at both the module and CPU levels and show that the approach is very effective in achieving low-power design.
To reduce the power consumed by computation, we propose a 3D hybrid architecture consisting of a CPU layer, a FPGA layer, and a DRAM layer. The FPGA layer is capable of supporting a variety of accelerators. We also exploit a fast communication mechanism that allows fast switches between these CPU and accelerators. Because FPGA accelerators consume much less power than out-of-order CPU cores, this architecture can achieve significant power reduction for computation compared with CPU-only systems.
To reduce the power consumed by communication, we focus on the state-of-the-art Single-cycle Multi-hop Asynchronous Repeated Traversal (SMART) network-on-chip. SMART allows a flit to traverse multiple routers within a single clock cycle. However, it suffers from large wire and energy overheads. We propose an SSR network that replaces long and overlapping broadcast wires with shorter wires and switches. It can reduce wire and power overheads of the SMART NoC drastically.