Princeton University

School of Engineering & Applied Science

Statistical Information Processing Platforms for Deep Nanoscale CMOS and Post-CMOS Era

Rami Abdallah
E-Quad, B205
Thursday, March 27, 2014 - 4:30pm

Next-generation ubiquitous computing is benefiting from Moore’s Law to promise new levels in immersion and seamless technology integration. However, this promise is being threatened today by the application complexity and device reliability challenges in deep nanoscale CMOS and post-CMOS fabric. This talk will introduce a communication-inspired statistical computing paradigm to enable the design of next-generation platforms that operate dramatically closer to the limits of achievable robustness-energy-performance envelope over highly unreliable device fabric. The proposed paradigm treats computing over unreliable devices similar to communicating information over noisy channels and employs techniques from estimation and detection theory to correct for errors in an optimal sense. The proposed design paradigm enable the correct operation of computing systems in presence of up to 70% hardware error rate while achieving 25% to 70% energy savings. This is illustrated in the design of Viterbi decoder, discrete-cosine-transform codec, and subthreshold biomedical processor. The results are supported through analysis, simulations, and IC prototype measurements. The proposed paradigm is further expanded to include the joint optimization of the power delivery subsystem and statistical information processing cores. This achieves 45% system energy savings and 2.3X improvement in power delivery efficiency.   
Rami Abdallah received the B. Eng. degree (with the highest distinction) from the American University of Beirut, Beirut, Lebanon, in 2006, and the M.S. and Ph.D. degrees from the University of Illinois at Urbana-Champaign, Urbana, IL, USA, in 2008 and 2012, respectively, all in electrical and computer engineering. Since June 2012, he has been with the Visual and Parallel Computing Group at Intel Corporation, Hillsboro, OR, USA, as a Silicon Architecture Engineer working on the back-end design of many-integrated core chips for cloud and high performance computing. From 2006 to 2012, he was a Research Assistant with the Coordinated Science Laboratory. During the summers of 2007, 2008, and 2009, he was with Texas Instruments Applications and Systems R&D Lab, where he was involved in the design of communication receivers for 4G systems and on-chip DC–DC converters for ultra-low-power medical platforms.
Dr. Abdallah was the recipient of the 2012 Low Power Design Contest Award at the International Symposium for Low Power Electronics and Design and the 2011 Best-in-Session Award at the SRC TECHCON conference. At Intel Corporation, he was the recipient of several spontaneous and group recognition awards. At the University of Illinois, he was the recipient of the Mac Van Valkenburg Outstanding Researcher Award in 2012, the Yi-Min Wang and Pi-Yu Chung Research Award in 2012, and the HKN Honor Society Scholarship in 2009.