Princeton University

School of Engineering & Applied Science

Efficient Device Simulation and Power Optimization Techniques for Novel Finfet Circuit Design

Speaker: 
Sourindra Chaudhuri
Date/Time: 
Thursday, January 15, 2015 - 1:30pm to 3:00pm

Abstract
Recently, multi-gate transistors have been gaining attention as an alternative to conventional
metal oxide semiconductor field-effect transistors (MOSFETs). Superior gate control
over the channel, smaller subthreshold leakage, and reduced susceptibility to process
variations are some of the key features that give multi-gate structures a competitive edge
over planar MOSFETs. Among various multi-gate structures, silicon-on-insulator (SOI)
FinFETs are promising owing to their ease of fabrication. This thesis first focuses on
developing efficient device simulation techniques to ease characterization of FinFET devices/
logic gates under process-voltage-temperature (PVT) variations. Next, it proposes
several power optimization techniques enabled by different implementation styles that are
unique to FinFETs.
Ideally, 3D device simulation should be done for accurate characterization of FinFET
devices and logic gates, but this is impractical due to the huge CPU time required for such
simulations. In this thesis, we address this issue by proposing a methodology to obtain
gate underlap (LUN)-adjusted 2D models for FinFETs that very accurately track 3D device
behavior. Thus, we achieve 3D simulation accuracy with 2D simulation efficiency. We also
show that 2D device models remain valid even under PVT variations. For the first time in
this thesis, we further show that the states obtained from quasi-stationary (QS) simulation
of a nominal device can assist in significantly reducing simulation time of similar devices
under process-voltage (PV) variations. When combined, such adjusted-assisted technique
makes PV analysis faster by few orders of magnitude.
This thesis also proposes techniques to optimize power consumption of FinFET based
circuits. First, we present a delay-constrained power optimization methodology in which
the negligible amount of leakage power consumed by asymmetric-workfunction shortedgate
(AWSG) cells plays a pivotal role. Further, for the first time, we analyze multiparameter
asymmetric shorted-gate FinFETs and illustrate their potential for implementing
logic gates and circuits that are both ultra-low-leakage and high-performance simultaneiii
ously. We show that logic gates and circuits based on asymmetric workfunction-underlap
shorted-gate (AWUSG) FinFETs provide higher performance at much less leakage power
as well as less area compared to gates/circuits based on traditional shorted-gate FinFETs.