Princeton University

School of Engineering & Applied Science

Exploring the System Hierarchy from Devices to On-Chip Communication

Speaker: 
Debajit Bhattacharya
Location: 
Engineering Quadrangle B327
Date/Time: 
Tuesday, September 6, 2016 - 12:00pm to 2:00pm

Abstract
Despite their significant advantages in electrostatics, FinFETs, the successor of planar CMOS beyond the 22 nm node, suffer from increased fringe capacitance because of the non-planar geometry. Recently, technology computer-aided design (TCAD)-assisted automation in structure synthesis followed by a transport analysis-based capacitance extraction approach has shown a lot of potential in terms of accuracy and computational efficiency. However, extending TCAD from the circuit level to the array level still poses a major computational challenge. In the first three chapters of the thesis, we attempt to address this challenge, also known as the many-device TCAD barrier challenge. In the first work in this category, we explore the design space of FinFET content-addressable memories (CAMs) and propose two capacitance-sensitive orthogonal layout styles for FinFET-based CAM design. In the second work, we extend and validate the TCAD-assisted capacitance extraction methodology to extract parasitic capacitances in a 10 GHz voltage-controlled oscillator. In the third work in this category, we extend the TCAD-assisted capacitance extraction framework to SRAM and logic arrays, proposing three methods to speed up capacitance extraction. The second emphasis of this thesis is on emerging monolithic 3D integration technology. For the first time, we explore the design possibilities for several FinFET-based ultra-high density monolithic 3D 6T and 8T SRAMs, taking detailed process variations into account. We propose a new 8T 3D FinFET SRAM bitcell that shows significant improvements in read stability and silicon footprint area without affecting writeability, when compared with the conventional 2D 6T SRAM bitcell. The third and final research direction of the thesis focuses on networks-on-chip (NoCs). Traditionally, analytical performance models have been used to speed up the extremely slow simulation/prototyping phase of modern NoC design. However, the currently available analytical models’ outdatedness forces NoC designers to rely on simulation/prototyping. In view of this, we propose a novel analytical NoC performance analysis methodology for modeling the state-of-the-art single-cycle multi-hop asynchronous repeated traversal (SMART) NoC that enables packets to partially or completely bypass routers from source to destination. To the best of our knowledge, this is the first work on analytical modeling of NoCs that enable bypassing of routers