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Niraj K. Jha

Prof. Jha joined the Department of Electrical Engineering at Princeton University as an assistant professor in 1987, became an associate professor in 1993, and a full professor in 1998. His research interests include power- and temperature-aware chip multiprocessor (CMP) and multiprocessor system-on-chip (MPSoC) design, design algorithms and tools for FinFETs, three-dimensional integrated circuit (3D IC) design, embedded system analysis and design, field-programmable gate arrays (FPGAs), digital system testing, computer security, and cyber-physical systems.

His current research projects are in the areas of FinFET-based circuit, memory, and CMP design; 3D MPSoCs; ultra-low-power FPGAs; on-chip interconnection networks; VLSI design for medical applications; temperature-aware test; embedded system security.

Steady miniaturization of transistors with each new generation of bulk CMOS technology has yielded continual improvement in the performance of digital circuits. The scaling of bulk CMOS, however, faces significant challenges in the future due to fundamental material and process technology limits. The primary obstacles to the scaling of bulk CMOS to the 22nm technology node include short-channel effects, sub-threshold leakage, and device-to-device variations. It is expected that the use of double-gate field-effect transistors (DG-FETs), the most popular among which are FinFETs, will be necessary to overcome these obstacles to scaling. Prof. Jha's group is actively investigating novel FinFET-based circuits, memories and computer architectures.

3D ICs are emerging as solutions to address the long interconnect and memory bandwidth problems. In addition, such ICs enable ``More than Moore's Law" applications that allow heterogeneous integration across their multiple layers, opening up exciting possibilities for innovative SoC design. Prof. Jha's group is investigating various 3D ICs that employ novel system designs comprising FPGAs, memories, embedded processors and RF circuitry.

Power consumption has become one of the most important metrics in evaluating a circuit today. This is due to a variety of requirements, such as prolonging battery lifetime in portable devices, reducing chip packaging and cooling costs, and increasing reliability, as well as due to environmental considerations. Prof. Jha's group has been researching low- power FPGAs, interconnection networks and CMPs. A related important problem is that of dynamic thermal management, which is also of interest to his group.

Security is emerging as an important concern in the embedded system area. Security of embedded systems is often compromised due to vulnerabilities in the ``trusted" software they execute. Security attacks exploit these vulnerabilities. Prof. Jha's group has been working on a hardware-assisted paradigm as well as virtualization to enhance embedded system security by detecting and preventing the execution of malware.

When testing an IC, if not enough care is taken, there is a chance that even a good die will get inadvertently damaged because of the high temperatures caused by test application. Although low-power test has a rich history, temperature-aware test is a new field. Prof. Jha's group is developing various temperature-aware test methodologies.

Prof. Jha is a Fellow of IEEE and ACM. He is currently serving as the Editor-in-Chief of IEEE Transactions on VLSI Systems and an Associate Editor of IEEE Transactions on Circuits and Systems I, IEEE Transactions on Computer-Aided Design, and Journal of Low Power Electronics. He has served as an Associate Editor of IEEE Transactions on Circuits and Systems II and Journal of Electronic Testing: Theory and Applications in the past. He has also served as the Program Chairman of the 1992 Workshop on Fault- Tolerant Parallel and Distributed Systems, the 2004 International Conference on Embedded and Ubiquitous Computing, and the 2010 International Conference on VLSI Design. He has served as the Director of the Center for Embedded System-on-a-chip Design funded by New Jersey Commission on Science and Technology. He is the recipient of the AT&T Foundation Award and NEC Preceptorship Award for research excellence, NCR Award for teaching excellence, and Princeton University Graduate Mentoring Award. He has co-authored four books titled Testing and Reliable Design of CMOS Circuits (Kluwer, 1990), High-Level Power Analysis and Optimization (Kluwer, 1998), Testing of Digital Systems (Cambridge University Press, 2003), and Switching and Finite Automata Theory, 3rd ed. (Cambridge University Press, 2009). He has also authored ten book chapters. He has authored or co-authored more than 330 technical papers. He has co-authored eight papers which have won the Best Paper Award at ICCD'93, FTCS'97, VLSID'98, DAC'99, PDCS'02, VLSID'03, CODES'06, and ICCD'09. A paper of his was selected for ``The Best of ICCAD: A collection of the best IEEE International Conference on Computer-Aided Design papers of the past 20 years,'' two papers by IEEE Micro Magazine as one of the top picks from the 2005 and 2007 Computer Architecture conferences, and two others as being among the most influential papers of the last 10 years at IEEE Design Automation and Test in Europe Conference. He has received 13 U.S. patents.