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Jiong Luo *03

Jiong Luo
Synopsys Inc.
Mountain View, CA

Contact Availability: OPEN2FACULTY

Ph.D: Electrical Engineering, 2003

Thesis: System-level power optimization for real-time distributed embedded systems

Advisor: Niraj Jha

Biography

Jiong Luo is a senior staff R&D engineer at Synopsys Inc., where she works in the optimization group of Design Compiler. Before she joined Synopsys, she was a PhD Student in Department of Electrical Engineering at Princeton University. She holds a PhD degree in Electrical Engineering from Princeton University, and an M.E. and a B.E. degree in Electronic Engineering from Tsinghua University.

She is involved in research and development work in the areas of energy-efficient computing, EDA (Electronic Design Automation) for integrated systems, register-transfer level (RTL) and physical synthesis, and system-level power optimization techniques.

Recent recognition of her work includes Synopsys Excellence Award 2009, for her significant contributions to Synopsys Physical Guidance feature for RTL and physical synthesis.