Larry Pearlstein *87
770 Township Line Rd.
Yardley, PA 18940, USA
Ph.D: Electrical Engineering, 1987
Thesis: Adaptive Linear Filters for Processing Sinusoidal Signals
Advisor: Bede Liu
Larry Pearlstein is a Multimedia Systems Architect at AMD. He has helped to create a low-cost ultra-high performance video processing architecture, which has been scaled to include as many as 20 processors. The processing architecture has been the basis for three chips, to date. His work at AMD has led to one US patent, and several patents pending.
Prior to joining AMD he was a Chief Researcher for Hitachi America's Digital Media and Systems Laboratory. During his tenure with Hitachi he served as Chairman of the Advanced Television Systems Committee (ATSC) Specialists Group on Video Coding (T3/S6). As Chairman he presided over the creation of the video compression standard used for transmitting High Definition Television in North America. He participated in the creation of the MPEG-2 video compression standard. He authored 40 US patents, and received the Hitachi America President's Award for his work.
Before joining Hitachi America he was Vice President of Engineering for BioAutomation, Inc., a biotech instrumentation start-up company and, before that, an Assistant Professor of Electrical Engineering at the University of Delaware.