Princeton University

School of Engineering & Applied Science

Naveen Verma

Associate Professor of Electrical Engineering

Director of Graduate Studies


Room: B226 Engineering Quadrangle
Phone: 609-258-1424
Email: nverma@princeton.edu
Webpage: Verma Lab: Systems for Sensing Physically Complex Signals

Curriculum Vitae

Education

  • Ph.D., Massachusetts Institute of Technology, 2009
  • M.Sc., Electrical Engineering Massachusetts Institute of Technology, 2005
  • B.A.Sc., Computer Engineering, University of British Columbia, 2003

Over the last four decades, the capabilities of integrated circuits (ICs) have expanded at an exponential rate according to Moore's Law. As a result, their application space has also expanded, from isolated server rooms to desktops to personal-area swarms to within the body. The pace has brought ICs to a point where they now face fundamental limits of energy, density, and performance. As a result, modern IC design requires new methods of scaling. Fortunately, since ICs have expanded into such a broad range of applications, there are many new opportunities to push their limits. These opportunities, however, are extremely diverse, requiring circuits that exploit the properties of new algorithms, new materials and devices, and new application characteristics. Our research focuses on analog and digital integrated circuits. Our emphasis is on developing system platforms for emerging applications, especially where considerable computation and instrumentation is required but energy is severely constrained. Important examples include implantable and wearable biomedical systems and remote sensing and processing network nodes. To drive this, there are two broad thrusts to our research: (1) application driven circuits and algorithms for ultra-low-power systems, and (2) platform components for low-power processing and communication in advanced and emerging technologies. By focusing on specific application domains, electronic systems can perform rich sensor acquisition and efficient algorithm computation. We aim to develop analog topologies to acquire diverse, multi-channel biomedical signals, and algorithm computation engines to extract specific correlations with physiological processes and conditions. Low-power processing and communication are critical means to reduce system power. To make their broad utilization increasingly viable, we aim to develop logic, connectivity circuits, and memory circuits (e.g., SRAM) to overcome emerging limitations in advanced technologies (e.g., nanometer CMOS) and alternate technologies (e.g., thin-film large-area electronics).

Honors and Awards

  • Alfred Rheinstein Faculty Award, Princeton School of Engineering and Applied Sciences (2012)
  • Princeton Innovation Forum 1st Place (2012)
  • Jack Kilby Outstanding Student Paper Award Int. Solid-State Circuits Conf. (2008)
  • Intel Foundation Ph.D. Fellowship Program Award Intel (2008)
  • NSERC Postgraduate Fellowship NSERC (2008)
  • DAC/ISSCC Student Design Contest Winner DAC/ISSCC (2006)

Selected Publications

  1. Y. Hu, W. Rieutort-Louis, J. Sanz-Robinson, K. Song, J. C. Sturm, S. Wagner and N. Verma, “High-resolution Sensing Skin for Structural-health Monitoring via Scalable Interfacing of Flexible Electronics with High-performance ICs,” to appear in Symp. VLSI Circuits, June 2012.

  2. L. Huang, W. Rieutort-Louis, Y. Hu, J. Sanz-Robinson, S. Wagner, J. C. Sturm and N. Verma, “Integrated All-silicon Thin-film Power Electronics on Flexible Sheets for Ubiquitous Wireless Charging Stations based on Solar-energy Harvesting,” to appear in Symp. VLSI Circuits, June 2012.

  3. M. Shoaib, N. K. Jha and N. Verma, ``Enabling Advanced Inference on Sensor Nodes through Direct use of Compressively-sensed Signals," IEEE Design Automation and Test in Europe Conf., March 2012.

  4. K. H. Lee, S.-Y. Kung and N. Verma, “Improving Kernel-energy Tradeoffs for Machine Learning in Implantable and Wearable Biomedical Applications,” Int. Conf. on Acoustics, Speech and Signal Processing, May 2011.

  5. A.P. Chandrakasan, D.C. Daly, D.F. Finchelstein, J. Kwong, Y.K. Ramadass, M.E. Sinangil, V. Sze, N.Verma, “Technologies for Ultra-Dynamic Voltage Scaling,” Proceedings of the IEEE, Jan. 2010.

  6. A.P. Chandrakasan, D.C. Daly, D.F. Finchelstein, J. Kwong, Y.K. Ramadass, M.E. Sinangil, V. Sze, N.Verma, “Technologies for Ultra-Dynamic Voltage Scaling,” to appear in Proceedings of the IEEE, 2010.

  7. M.E. Sinangil, N. Verma, A.P. Chandrakasan, “A Reconfigurable Ultra-Dynamic Voltage Scalable (UDVS) SRAM in 65nm”, IEEE J. Solid-State Circuits, Nov. 2009.

  8. N. Verma, and A. P. Chandrakasan, “A High-Density 45nm SRAM Using Small-Signal Non-Strobed Regenerative Sensing,” IEEE J. Solid-State Circuits, ISSCC Special Issue, Jan. 2009.

  9. J. Kwong, Y. Ramadass, N. Verma, and A. Chandrakasan, “A 65nm Sub-Vt Microcontroller with Integrated SRAM and Switch Capacitor DC-DC Converter,” IEEE J. Solid-State Circuits, ISSCC Special Issue, Jan 2009.

  10. A.P. Chandrakasan, N. Verma, and D. Daly, “Ultra Low Power Electronics for Biomedical Applications,” to appear in Annual Review of Biomedical Engineering, Aug. 2008.

  11. N. Verma and A. P. Chandrakasan, “A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy,” IEEE J. Solid-State Circuits, ISSCC Special Issue, Jan. 2008.

  12. N. Verma, J. Kwong and A. P. Chandrakasan, “Nanometer MOSFET Variation in Minimum Energy Sub-Threshold Circuits,” IEEE Trans. Elect. Devices, Jan. 2008.

  13. N. Verma and A. P. Chandrakasan, “An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes,” IEEE J. Solid-State Circuits, June 2007.

  14. B. H. Calhoun, D. C. Daly, N. Verma, D. F. Finchelstein, D. D. Wentzlaff, A. Wang, S.-H. Cho, and A. P. Chandrakasan, “Design Considerations for Ultra-Low Energy Wireless Microsensor Nodes,” IEEE Transactions on Computers, June 2005.