Princeton University

School of Engineering & Applied Science

Niraj Jha

Professor of Electrical Engineering

Room: B220 Engineering Quadrangle
Phone: 609-258-4754
Webpage: Jha Lab: FinFET and Embedded Security Lab


  • Ph.D., University of Illinois at Urbana-Champaign, 1985
  • M.S., in Electrical Engineering, State University of New York at StonyBrook, 1982
  • B.Tech., in Electronics & Electrical Communication Engineering, Indian Institute of Technology, Kharagpur, India, 1981

I joined the Department in 1987 and have been a full professor since 1998. My research interests include power- and temperature-aware chip multiprocessor (CMP) and multiprocessor system-on-chip (MPSoC) design, design algorithms and tools for FinFETs, three-dimensional integrated circuit (3D IC) design, embedded system analysis and design, field-programmable gate arrays (FPGAs), digital system testing, computer security, quantum circuit design, and energy-efficient buildings. My current research projects are in the areas of:

  • FinFET-based circuit, memory, and CMP design
  • 3D CMPs
  • ultra-low-power FPGAs
  • on-chip interconnection networks
  • very-large-scale integration (VLSI) design for medical applications
  • temperature-aware tests
  • embedded system security
  • quantum logic
  • sensors for reducing energy consumed in buildings

With each new generation of bulk complementary metal-oxide semiconductor (CMOS) technology, steady miniaturization of transistors has yielded continual improvement in the performance of digital circuits. The scaling of bulk CMOS, however, faces significant challenges in the future due to fundamental material and process technology limits. The primary obstacles to the scaling of bulk CMOS to the 22nm technology node include short-channel effects, sub-threshold leakage, and device-to-device variations. It is expected that the use of double-gate field-effect transistors (DG-FETs), the most popular of which are FinFETs, will be necessary to overcome these obstacles to scaling. My group is actively investigating novel FinFET-based circuits, memories, and computer architectures. 3D ICs are emerging as solutions to the problems of long interconnect and memory bandwidth. In addition, such ICs enable “More than Moore's Law” applications that allow heterogeneous integration across their multiple layers, opening up exciting possibilities for innovative SoC design. We are investigating various 3D ICs that employ novel system designs comprising embedded processors, RF circuitry, FPGAs, and memories. Power consumption has become one of the most important metrics in evaluating a circuit today. This is due both to environmental considerations and to a variety of technical requirements such as prolonging battery life in portable devices, reducing chip packaging and cooling costs, and increasing reliability. To that end, my group has been researching low-power FPGAs, interconnection networks, and CMPs. We are also interested in the related important problem of dynamic thermal management. Security is emerging as an important concern in the embedded system area. Security of embedded systems is often compromised due to vulnerabilities in the “trusted” software they execute. Security attacks exploit these vulnerabilities. My group has been working on a hardware-assisted paradigm as well as virtualization to enhance embedded system security by detecting and preventing the execution of malware. If not enough care is taken when testing an IC, even a good die may be inadvertently damaged by the high temperatures caused by test application. Although low-power test has a rich history, temperature-aware test is a new field. We are currently developing various temperature-aware test methodologies. The quest for quantum computers is gathering steam. Various quantum algorithms have been developed that show speeds orders of magnitude above those of classical computing. My group is interested in automatically obtaining optimized quantum logic circuits from these quantum algorithms. Energy consumption has also become an important issue, especially from the point of view of carbon dioxide emissions. In the U.S., buildings consume 40% of the total energy. Thus, reducing the energy consumed in buildings can have a substantial national impact. My group is developing various types of sensors to reduce the electricity/heating costs in buildings. I am a fellow of IEEE and the Association for Computing Machinery (ACM), and am currently serving as the Editor-in-Chief of IEEE Transactions on VLSI Systems, the Journal of Low Power Electronics, and the Journal of Nanotechnology. In the past I have served as an Associate Editor of IEEE Transactions on Circuits and Systems I & II, IEEE Transactions on Computer-Aided Design, and the Journal of Electronic Testing: Theory and Applications. I have served as the Program Chairman of the 1992 Workshop on Fault-Tolerant Parallel and Distributed Systems, the 2004 International Conference on Embedded and Ubiquitous Computing, and the 2010 International Conference on VLSI Design. I’ve also served as the Director of the Center for Embedded System-on-a-Chip Design funded by the New Jersey Commission on Science and Technology. I am the recipient of the AT&T Foundation Award and NEC Preceptorship Award for research excellence, the NCR Award for teaching excellence, and the Princeton University Graduate Mentoring Award. I have co-authored four books: Testing and Reliable Design of CMOS Circuits (Kluwer, 1990), High-Level Power Analysis and Optimization (Kluwer, 1998), Testing of Digital Systems (Cambridge University Press, 2003), and Switching and Finite Automata Theory, 3rd ed. (Cambridge University Press, 2009). I have also authored or co-authored ten book chapters and more than 350 technical papers. Nine of my co-authored papers have won the Best Paper Award at various conferences. My papers have also been selected for “The Best of ICCAD: A collection of the best IEEE International Conference on Computer-Aided Design papers of the past 20 years,” by IEEE Micro Magazine as top picks from the 2005 and 2007 Computer Architecture conferences, and two were included among the most influential papers of the last 10 years at the IEEE Design Automation and Test in Europe Conference. I have received 13 U.S. patents.

Honors and Awards

  • Best Paper Award at IEEE International Conference on Computer Design (2009)
  • Best Paper Award at IEEE/ACM International Conference on Hardware/Software Co-Design and System Synthesis (2006)
  • Best Paper Award at IASTED International Conference on Parallel and Distributed Computing and Systems (2002)
  • Best Paper Award at IEEE Design Automation Conference (1999)
  • Best Paper Award at International Conference on VLSI Design (1998)
  • Princeton University Graduate Mentoring Award (2004)
  • NEC Preceptorship Award for Research Excellence, School of Engineering & Applied Science, Princeton University (1992)
  • NCR Award for Teaching Excellence, Princeton University (1990)
  • AT&T Foundation Award for Research Excellence (1990)
  • NSF Engineering Initiation Award (1987)

Selected Publications

  1. P. Mishra, A. Bhoj, and N. K. Jha, “Die-level leakage power analysis of FinFET circuits considering process variations,” IEEE Int. Symp. on Quality Electronic Design, Mar. 2010;

  2. P. Mishra and N. K. Jha, “Low-power FinFET circuit synthesis using surface orientation optimization,” IEEE Design Automation & Test in Europe Conference, Mar. 2010;

  3. N. Agarwal, L.-S. Peh, and N. K. Jha, “In-network coherence filtering: Snoopy coherence without broadcasts,” IEEE Int. Symp. on Microarchitecture, Dec. 2009;

  4. M. Simsir and N. K. Jha, “Thermal characterization of BIST, scan design and sequential test methodologies,” IEEE Int. Test Conference, Nov. 2009;

  5. C.-Y. Lee and N. K. Jha, “FinFET-based dynamic power management of on-chip interconnection networks through adaptive back-gate biasing,” IEEE Int. Conference on Computer Design, Oct 2009;

  6. A. Bhoj and N. K. Jha, “Pragmatic design of gated-diode FinFET DRAMs,” IEEE Int. Conf.on Computer Design, Oct. 2009;

  7. N. Agarwal, T. Krishna, L.-S. Peh, and N. K. Jha, “GARNET: A detailed on-chip network model inside a full-system simulator,” IEEE Int. Symp. on Performance Analysis of Systemsand Software, Apr. 2009.

  8. C. Li, A. Raghunathan, and N. K. Jha, “An architecture for secure software defined radio,”IEEE Design Automation and Test in Europe Conf., Mar. 2009.

  9. N. Agarwal, L.-S. Peh, and N. K. Jha, “In-network snoop ordering (INSO): Snoopy coherenceon unordered interconnects,” IEEE Int. Symp. on High-Performance Computer Architecture,Feb. 2009.

  10. A. Kumar, L.-S. Peh, and N. K. Jha, “Token flow control,” IEEE Int. Symp. on Microarchitecture, Oct. 2008.

  11. N. Aaraj, A. Raghunathan, and N. K. Jha, “Dynamic binary instrumentation based framework for malware (virus) defense,” Conf. on Detection of Intrusions and Malware & Vulnerability Assessment, July 2008.

  12. P. Mishra, A. Muttreja, and N. K. Jha, “Evaluation of multiple supply and threshold voltages for low-power FinFET circuit synthesis,” IEEE/ACM Int. Symp. on Nanoscale Architectures, June 2008.

  13. A. Muttreja, P. Mishra, and N. K. Jha, “Threshold voltage control through multiple supply voltages for power-efficient FinFET interconnects,” Int. Conf. on VLSI Design, Jan. 2008.

  14. M. Simsir, S. Cadambi, F. Ivancic, M. Roetteler, and N. K. Jha, “Fault-tolerant computing usinga hybrid nano-CMOS architecture,” Int. Conf. on VLSI Design, Jan. 2008.

  15. A. Muttreja, S. Ravi, and N. K. Jha, “Variability-tolerant register-transfer level synthesis,” Int.Conf. on VLSI Design, Jan. 2008.