Princeton University

School of Engineering & Applied Science

Niraj Jha

Professor of Electrical Engineering


Room: B220 Engineering Quadrangle
Phone: 609-258-4754
Email: jha@princeton.edu
Webpage: Jha Lab: FinFET and Embedded Security Lab

Education

  • Ph.D., University of Illinois at Urbana-Champaign, 1985
  • M.S., in Electrical Engineering, State University of New York at StonyBrook, 1982
  • B.Tech., in Electronics & Electrical Communication Engineering, Indian Institute of Technology, Kharagpur, India, 1981

I joined the Department in 1987 and have been a full professor since 1998. Our research interests include smart healthcare, Internet-of-Things (IoT), machine learning, cybersecurity, embedded computing, energy-efficient computing, and monolithic 3D IC design. Our current research projects are in the areas of:

  • Use of machine learning for disease diagnosis
  • Neural network synthesis
  • Energy-efficient inference
  • IoT security
  • Monolithic 3D IC design: circuits, architectures, applications

The Internet-of-Things (IoT) era promises hundreds of billions of devices or physical objects connected to the Internet.  These objects include sensors, actuators, and processing elements that help us gather data, make intelligent decisions, and optimize processes. IoT is expected to have a potential economic impact of $3-6 trillion per year by 2025, with $1-2.5 trillion of this economic impact (its largest fraction) coming from smart healthcare applications.  These applications will be enabled by wearable medical sensors (WMSs) that will transmit their information to a personal health hub, such as a smartphone or smartwatch.  The sensors and the health hub form a body-area network (BAN). The BAN will communicate with a health server over the Internet, making a complete personal healthcare system possible.  The doctors can communicate with the health server to keep track of an individual’s health. However, many challenges remain in making this vision a reality. Our group is exploring the possibility of diagnosing various diseases using WMSs and machine learning ensembles. This methodology can be further facilitated through energy-efficient inference on WMSs. Energy-efficient inference is made possible on sensor nodes by exploiting sparsity, which is a characteristic of a signal that allows us to represent information efficiently. We have investigated an approach that enables efficient representations based on sparsity to be utilized throughout a signal processing system, with the aim of reducing the energy and/or resources required for computation, communication, and storage. Such intelligent WMSs can be expected to be an important pillar of smart healthcare.  We have explored how energy- and storage-efficient continuous long-term personal health monitoring is possible. Finally, we are investigating security issues associated with smart healthcare.
Neural networks have begun to have pervasive impact in diverse areas.  However, synthesis of neural networks remains an art.  We are developing methodologies and tools to automatically synthesize neural networks from provided datasets with the aim of meeting state-of-the-art classification accuracy targets while reducing hardware resources by two orders of magnitude.
We are also interested in monolithic 3D IC design, from devices to systems.  The projects involve design of processor cores, networks-on-chip, SRAMs, memory-processor interfaces, and chip multiprocessors, using a hybrid of various design styles: transistor-level monolithic, gate-level monolithic, and block-level monolithic, and design automation methodologies and tools to support such designs.
I am a fellow of IEEE and ACM. I have served as the Editor-in-Chief of IEEE Transactions on VLSI Systems. I am currently serving as an Associate Editor of IEEE Transactions on Multi-Scale Computing Systems and the Journal of Low Power Electronics. In the past, I have served as an Associate Editor of IEEE Transactions on Circuits and Systems I & II, IEEE Transactions on Computer-Aided Design, IEEE Transactions on Computers, IEEE Transactions on VLSI Systems, Journal of Nanotechnology, and the Journal of Electronic Testing: Theory and Applications. I have served as the Program Chairman of the 1992 Workshop on Fault-Tolerant Parallel and Distributed Systems, the 2004 International Conference on Embedded and Ubiquitous Computing, and the 2010 International Conference on VLSI Design. I have also served as the Director of the Center for Embedded System-on-a-Chip Design funded by the New Jersey Commission on Science and Technology, and as the Associate Director of the Andlinger Center for Energy and the Environment.  I am a recipient of the AT&T Foundation Award and NEC Preceptorship Award for research excellence, the NCR Award for teaching excellence, six Commendations for Outstanding Teaching, the Princeton University Graduate Mentoring Award, and the Distinguished Alumnus Award from I.I.T., Kharagpur. I have co-authored or co-edited five books: Testing and Reliable Design of CMOS Circuits (Kluwer, 1990), High-Level Power Analysis and Optimization (Kluwer, 1998), Testing of Digital Systems (Cambridge University Press, 2003), Switching and Finite Automata Theory, 3rd ed. (Cambridge University Press, 2009), and Nanoelectronic Circuit Design (Springer, 2010). I have also authored or co-authored 15 book chapters and more than 430 technical papers. 20 of my co-authored papers have won various awards or award nominations. These include a paper selected for “The Best of ICCAD: A collection of the best IEEE International Conference on Computer-Aided Design papers of the past 20 years,” two papers by IEEE Micro Magazine as top picks from the 2005 and 2007 Computer Architecture conferences, and two papers as being among the most influential papers of the last 10 years at the IEEE Design Automation and Test in Europe Conference. I have received 17 U.S. patents.

Honors and Awards

  • Distinguished Alumnus Award, I.I.T., Kharagpur, India (2014)
  • Princeton University Graduate Mentoring Award (2004)
  • ACM Fellow (2003)
  • IEEE Fellow (1998)
  • NEC Preceptorship Award for Research Excellence, School of Engineering & Applied Science, Princeton University (1992)
  • NCR Award for Teaching Excellence, Princeton University (1990)
  • AT&T Foundation Award for Research Excellence (1990)
  • NSF Engineering Initiation Award (1987)

Selected Publications

  1. H. Yin and N. K. Jha, ``A hierarchical health decision support system based on wearable medical sensors and machine learning ensembles," IEEE Trans. on Multi-Scale Computing Systems, May 2017;

  2. A. O. Akmandor and N. K. Jha, ``Keep the stress away with SoDA: Stress detection and alleviation system," IEEE Trans. on Multi-Scale Computing Systems, May 2017; 

  3. A. M. Nia, S. Sur-Kolay, A. Raghunathan, and N. K. Jha, ``CABA: Continuous authentication based on BioAura," IEEE Trans. on Computers, May 2017;

  4. A. Mosenia, S. Sur-Kolay, A. Raghunathan, and N. K. Jha, ``Wearable medical sensor-based system design: A survey," IEEE Trans. on Multi-Scale Computing Systems, Apr.-June 2017;

  5. A. M. Nia and N. K. Jha, ``A comprehensive study of security of Internet-of-Things," IEEE Trans. on Emerging Topics in Computing, Sept. 2016;

  6. A. M. Nia, S. Sur-Kolay, A. Raghunathan, and N. K. Jha, ``Physiological information leakage: A new frontier in health information security," IEEE Trans. on Emerging Topics in Computing, July-Sept. 2016;

  7. A. M. Nia, M. Mozaffari-Kermani, S. Sur-Kolay, A. Raghunathan, and N. K. Jha, ``Energy-efficient long-term continuous personal health monitoring," IEEE Trans. on Multi-Scale Computing Systems, Apr.-June 2015;

  8. M. Zhang, A. Raghunathan, and N. K. Jha, ``Trustworthiness of medical devices and body area networks," Proc. of IEEE, Aug. 2014;

  9. A. Mosenia, X. Dai, P. Mittal, and N. K. Jha, ``PinMe: Tracking a smartphone user around the world," accepted for publication in IEEE Trans. on Multi-Scale Computing Systems;

  10. M. Mozaffari-Kermani, S. Sur-Kolay, A. Raghunathan, and N. K. Jha, ``Systematic poisoning attacks on and defenses for biomedical machine learning," IEEE Journal of Biomedical and Health Informatics, Nov. 2015;

  11. M. Shoaib, N. K. Jha, and N. Verma, ``Signal processing with direct computations on compressively-sensed data," IEEE Trans. on VLSI Systems, Jan. 2015;

  12. J. Lu, N. Verma, and N. K. Jha, ``Compressed signal processing on Nyquist-sampled signals," IEEE Trans. on Computers, Nov. 2016;

  13. D. Bhattacharya and N. K. Jha, ``Ultra-high density monolithic 3-D FinFET SRAM with enhanced read stability," IEEE Trans. on Circuits and Systems I, Aug. 2016;

  14. Y. Yu and N. K. Jha, ``Energy-efficient monolithic 3D on-chip memory architectures," accepted for publication in IEEE Transactions on Nanotechnology;

  15. X. Chen and N. K. Jha, ``A 3D CPU-FPGA-DRAM hybrid architecture for low-power computation," IEEE Trans. on VLSI Systems, May 2016.