Device scaling, an enabler of faster and more powerful processors for decades, has become challenging due to physical limits and manufacturing costs. Thus, we need newer approaches for low-power and high-performance designs for next generation computing technologies. In this talk, we focus on FinFET-based static random access memory (SRAM) and hybrid monolithic 3-D integrated circuit (IC) design.
First, we will discuss the design of area-efficient, low-power, and high-performance SRAM cells, which often occupy more than half the die area in processors. We will investigate two approaches: multi-parameter asymmetric (MPA) FinFET-based and 3-D transistor-level monolithic (TLM) SRAM design. In the first approach, we will use FinFETs with up to three asymmetries to address SRAM challenges such as high leakage power, read-write conflict, and width quantization at once. In the second approach, we will present two new area-efficient 3-D monolithic 8T SRAM cells that consist of four n-type and four p-type transistors. The proposed cells provide superior read performance and power efficiency when compared to other 2-D/3-D SRAM cells.
Second, we will explore the benefits of monolithic 3-D design from the circuit to the multi-core system level. We will focus on hybrid monolithic (HM) designs, which combine modules implemented in different monolithic styles to utilize their advantages. We will discuss a 3-D HM floorplanner, gate-level placement methodology, and modeling tools for logic, memory, and NoC modules. We have integrated these tools into McPAT-monolithic, an area/timing/power architectural modeling framework we have developed for HM multi-core systems.